| PART |
Description |
Maker |
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| K4E661612EK4E641612E |
4M x 16bit CMOS Dynamic RAM with Extended Data Out Data Sheet
|
Samsung Electronic
|
| F-137G |
High Frequency Data Line Filter 3 Coils 6 Data Lines
|
Rhombus Industries Inc.
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| AD1801JST |
1400 kbps DATA, MODEM-DATA/FAX/VOICE, PQFP128 TQFP-128
|
Analog Devices, Inc.
|
| DSK4D263238D K4D263238D K4D263238D-QC40 K4D263238D |
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
|
SAMSUNG SEMICONDUCTOR CO. LTD.
Samsung Electronic
SAMSUNG[Samsung semiconductor]
|
| HI-8785PSTF HI-8783 HI-8783_06 HI-8783PDI HI-8783P |
ARINC INTERFACE DEVICE 8 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
| MC68HC908JB12 MC68HC908JB12DW MC68HC908JB12JDW MC6 |
Addendum to MC68HC908JB16 Technical Data
This section updates data sheet information and introduces the 20-pin SOIC
|
FREESCALE[Freescale Semiconductor, Inc]
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
| SDA006 SDA006-7 |
Data Line Protection
DATA BUS TRANSIENT SUPPRESSOR/3-PHASE FULL WAVE BRIDGE RECTIFIER
|
Dionics Inc.
DIODES[Diodes Incorporated]
|
| W972GG6JB W972GG6JB-25 |
16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
